Field
The present disclosure relates to a display device and a driving method thereof, and more particularly, to a display device in which a leakage current is generated when power supplied from a system board is turned off.
Description of the Related Art
With the development of the information society, various demands for display devices configured to display an image have been increasing. Accordingly, in recent years, various flat panel display (FPD) devices configured to reduce a weight and a volume of a cathode ray tube (CRT) have been developed and commercialized. Various FPD devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) display device are being used.
An LCD of an active matrix driving type includes a thin film transistor (hereinafter, referred to as “TFT”) as a switching element in each pixel. The LCD can be manufactured to be smaller than the CRT and thus may be applied to display units of portable information appliances, office equipment, computers, etc. Further, the LCD can be applied to televisions and thus is rapidly replacing the CRT.
A user's reliability in a display device becomes important. In particular, there have recently been cases where a leakage current is introduced into a system board of a display device and some functions of the display device cannot be performed.
FIG. 1 is a block diagram schematically showing a system board and a timing controller of a display device of the related art. Hereinafter, the display device of the related art will be described in detail with reference to the accompanying drawings.
Referring to FIG. 1, the display device includes a display panel (not shown), a system board 110, a level shifter 120, a timing controller 130, and a power supply unit 140.
The display panel may be a liquid crystal display panel configured to display an image using liquid crystals. The liquid crystal display panel includes a liquid crystal layer injected between two glass substrates bonded to each other with a space.
The system board 110 includes image data for displaying an image on the display panel, a clock signal for generating a signal required to drive the display panel, and an input voltage VIN. The image data and the clock signal are transmitted to the timing controller 130. The input voltage VIN is supplied to the power supply unit 140 at a level of 12 V.
The system board 110 includes a system sound processing unit 111 controlling sounds of the display device. The system sound processing unit 111 is driven in response to a signal transmitted from the timing controller 130.
The power supply unit 140 is supplied with the input voltage VIN from the system board 110 and generates a voltage required to drive a driving circuit such as the timing controller 130. Voltages relating to a driving of the timing controller 130 are a first voltage VCC1 and a second voltage VCC2. The first voltage VCC1 has a level of 2.5 V, and the second voltage VCC2 has a level of 1.2 V.
The timing controller 130 generates signals required to drive the display panel in response to a clock signal input from the system board 110. The signals of the timing controllers 130 include a gate driving signal GDC, a data driving signal DDC, a system sound control signal SSC, and a backlight driving control signal BDC. The signals of the timing controller 130 have levels of 2.5 V and 1.2 V. The system sound control signal SSC of the timing controller 130 is transmitted to the system board 110 under predetermined conditions and controls sounds of the display device 100. The system sound control signal SSC is one of signals generated by the timing controller 130 and has a level of 2.5 V.
Level shifters 120a and 120b are configured to convert the system sound control signal SSC and the backlight driving control signal BDC input from the timing controller 130 into proper voltage levels and then transmit them to the system board 110 and a backlight (not shown).
Referring to FIG. 1, the level shifters 120a and 120b include an enable pin Enable Pin connected to a ground GND. The enable pin Enable Pin is a terminal set to output an input signal as a signal SSC_out having a level of 3.3 V only when a voltage level of a signal SSC_in input into the level shifters 120a and 120b is in a low state.
FIG. 2 is an exemplary diagram showing level shifter waveforms and generation of leakage currents when the display device of the related art is turned off. FIG. 2 shows that when the input voltage VIN supplied from the system board 110 is turned from on to off, the input voltage VIN is not immediately and completely turned to an off state. This is because even if the input voltage VIN is turned off, a transmission line for transmitting the input voltage VIN has a high capacitance and thus a falling time of the input voltage VIN becomes long. The falling time is about 1000 ms. Therefore, even if the input voltage VIN is turned off, signals having certain voltage levels VCC1 and VCC2 are not disabled but remain in the timing controller 130.
Referring to FIG. 2, a voltage level of the signals remaining in the timing controller 130 is 2.5 V. This voltage level may be converted into 3.3 V and then transmitted to the system board 110. As a result, although the display device 100 is turned off, an unnecessary leakage current is introduced into the system board 110 and may cause a circuit damage or malfunction.